Storage device and storage unit

ABSTRACT

A storage device includes: a first electrode; a storage layer including an ion source layer; and a second electrode. The first electrode, the storage layer, and the second electrode are provided in this order. The ion source layer contains a movable element, and has a volume resistivity of about 150 mΩ·cm to about 12000 mΩ·cm both inclusive.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a continuation application of U.S. patentapplication Ser. No. 13/912,996, filed on Jun. 7, 2013 which claims thebenefit of priority from prior Japanese Patent Application No.2012-137588 filed in the Japan Patent Office on Jun. 19, 2012, theentire content of which is hereby incorporated by reference.

BACKGROUND

The present disclosure relates to a storage device and a storage unitthat store information by change in electrical characteristics of astorage layer that includes an ion source layer.

As semiconductor non-volatile memories for data storage, NOR-type orNAND-type flash memories have been generally used. Although a memorydevice and a driving transistor have been miniaturized in order toincrease the capacity of a semiconductor non-volatile memory, thelimitation in miniaturization has been pointed out since a high-voltageis necessary for writing and erasing and the number of electrons to beinjected into the floating gate is limited.

Currently, resistance change memories such as a ReRAM (resistance randomaccess memory) and a PRAM (phase-change random access memory) have beenproposed as next generation non-volatile memories capable of breakingthrough the limitation in miniaturization (for example, see JapaneseUnexamined Patent Application Publication No. 2006-196537 and Waser etal., Advanced Material, 21, p. 2932 (2009)). Such memories have a simplestructure in which a resistance change layer is disposed between twoelectrodes, and it is considered that atoms or ions transfer due to heator an electric field to form a conduction path, and thus the resistancevalue of the resistance change layer is changed, thereby performingwriting and erasing.

A multi-value of a memory is an alternative way to increase the capacityof the memory in which writing and erasing are performed using theresistance change besides the miniaturization of the memory as describedabove. Allowing the multi-value of the memory, in other words, allowinga multi-value recording of 2 bits (4 values), 3 bits (8 values) etc. perdevice increases the capacity two-fold, three-fold, and so on.

SUMMARY

To achieve the multi-value recording, it is necessary to perform writingof a plurality of conductance values. However, a memory includes aplurality of storage devices, and it is difficult to control anduniformize writing conductance values of all devices under respectivewriting conditions, and therefore there is an issue that a variation inconductance value between devices is easily caused.

It is desirable to provide a storage device and a storage unit thatreduce a variation in conductance value between a plurality of devices.

A storage device according to an embodiment of the present technologyincludes: a first electrode; a storage layer including an ion sourcelayer; and a second electrode. The first electrode, the storage layer,and the second electrode are provided in this order. The ion sourcelayer contains a movable element, and has a volume resistivity of about150 mΩ·cm to about 12000 mΩ·cm both inclusive.

In the storage device according to the above-described embodiment of thepresent technology, when a voltage pulse or current pulse is applied toa device at an initial state (high resistance state) in a “positivedirection” (for example, a negative potential on the first electrodeside and a positive potential on the second electrode side), themetallic element in the ion source layer may be ionized and diffusedinto the storage layer (for example, into the resistance change layer),or oxygen ions may transfer to generate an oxygen defect in theresistance change layer. Consequently, a low-resistance section(conduction path) in a low oxidation state may be formed in the storagelayer, and a resistance of the resistance change layer is decreased(record state). When a voltage pulse is applied to a device in thelow-resistance state in a “negative direction” (for example, a positivepotential on the first electrode side and a negative potential on thesecond electrode side), metal ions in the resistance change layer maytransfer into the ion source layer, or the oxygen ions may transfer fromthe ion source layer, and the oxygen defect at the conduction pathportion is decreased. Consequently, the conduction path includingmetallic element disappears, and a state where the resistance changelayer has a high resistance (initial state or erase state) isestablished.

Here, the ion source layer contains the movable element and has thevolume resistivity of about 150 mΩ·cm to about 12000 mΩ·cm bothinclusive. Hence, controllability of a writing conductance value under apredetermined writing condition is improved.

A storage unit according to an embodiment of the present technology isprovided with a plurality of storage devices and a pulse applier thatselectively applies one of a voltage pulse and a current pulse to thestorage devices. The storage devices each include: a first electrode; astorage layer including an ion source layer; and a second electrode. Thefirst electrode, the storage layer, and the second electrode areprovided in this order. The ion source layer contains a movable element,and has a volume resistivity of about 150 mΩ·cm to about 12000 mΩ·cmboth inclusive.

According to the storage device and the storage unit of theabove-described embodiments of the present technology, the ion sourcelayer contains the movable element, and has the volume resistivity ofabout 150 mΩ·cm to about 12000 mΩ·cm both inclusive. Therefore,controllability of a conductance value under a predetermined writingcondition is improved, and it is possible to reduce a variation inwriting conductance value between a plurality of devices.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary, and are intended toprovide further explanation of the technology as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the disclosure, and are incorporated in and constitutea part of this specification. The drawings illustrate embodiments and,together with the specification, serve to explain the principles of thetechnology.

FIG. 1 is a sectional view showing a configuration of a storage deviceaccording to an embodiment of the present disclosure.

FIG. 2 is a characteristic diagram illustrating a variation inconductance value in an existing example.

FIG. 3 is a characteristic diagram illustrating measured values andaverage values of the conductance values in the existing example.

FIG. 4 is a sectional view showing a configuration of a memory cellarray using the storage device of FIG. 1.

FIG. 5 is a plan view of the memory cell array illustrated in FIG. 4.

FIG. 6 shows characteristic diagrams of measured values and averagevalues of conductance values of respective experiments according to anembodiment of the present disclosure (Experiments 1-1 to 1-6).

FIG. 7 is a characteristic diagram for comparing writing conductancevalues in the respective experiments.

FIG. 8 is a characteristic diagram for comparing standard deviations ofthe writing conductance values in 30 bits in the respective experiments.

FIG. 9 is a characteristic diagram showing a relationship between thestandard deviations of the writing conductances and the average valuesof the writing conductance values in 30 bits in the respectiveexperiments.

DETAILED DESCRIPTION

In the following, an embodiment of the present disclosure is describedin the following order with reference to the drawings.

1. Embodiment

1-1. Storage Device

1-2. Storage Unit

2. Working Example

Embodiment 1-1. Storage Device

FIG. 1 shows a cross-sectional configuration of a storage device 1according to an embodiment of the present disclosure. The storage device1 includes a lower electrode 10 (first electrode), a storage layer 20that includes an ion source layer 21, and an upper electrode 30 (secondelectrode) in this order.

The lower electrode 10 may be provided on a substrate 41, which may bemade of silicon and may be formed with a CMOS (complementary metal oxidesemiconductor) circuit, and may serve as a connecting section forconnection to the CMOS circuit as described later (FIG. 4), for example.The lower electrode 10 may be made of a wiring material for use insemiconductor processes. Examples of the wiring material may includetungsten (W), tungsten nitride (WN), copper (Cu), aluminum (Al),molybdenum (Mo), tantalum (Ta), and silicide. When the lower electrode10 is made of a material such as Cu which may cause ion conduction by anelectric field, a surface of the lower electrode 10 made of Cu or thelike may be covered with a material less likely to cause ion conduction,heat diffusion, or the like, such as W, WN, titanium nitride (TiN), ortantalum nitride (TaN).

The storage layer 20 has a structure in which the ion source layer 21and a resistance change layer 22 are laminated in order from the upperelectrode 30 side. The ion source layer 21 includes an element (movableelement) that forms a conduction path in the resistance change layer 22.

In the present embodiment, the ion source layer 21 includes the movableelement as described above, and is provided in contact with the upperelectrode 30. The movable element is positively ionized or negativelyionized by application of an electric field and transfers into theresistance change layer 22, thereby forming the conduction path.Examples of the movable element to be positively ionized may includetransition metal elements, in particular, metallic elements belonging toGroup 4 elements (titanium (Ti), zirconium (Zr), and hafnium (Hf)),Group 5 elements (vanadium (V), niobium (Nb), and tantalum (Ta)), andGroup 6 elements (chromium (Cr), molybdenum (Mo), and tungsten (W)) inthe Periodic Table. Examples of the movable element to be negativelyionized may include Group 16 elements, in particular, chalcogen elementssuch as tellurium (Te), sulfur (S), and selenium (Se) in the PeriodicTable. In addition, oxygen (O) may also be used. It is to be noted that,in the present embodiment, the ion source layer 21 contains one or twoor more of such movable elements.

Preferably, the ion source layer 21 of the present embodiment may have avolume resistivity of about 150 mΩ·cm to about 12000 mΩ·cm bothinclusive. In the storage device 1 which performs writing and erasingwith use of a resistance change as in the present embodiment, the volumeresistivity of the ion source layer 21 greatly influencescontrollability of an intermediate resistance value, or in other words apredetermined writing conductance value, which is important forachieving multi-value recording.

In the ion source layer 21, the above-mentioned transition metalelement, the chalcogen element, and oxygen combine with each other andform a metal chalcogenide oxide layer. The metal chalcogenide oxidelayer mainly has an amorphous structure, and serves as an ion supplysource. The conduction path including the above-mentioned transitionmetal element is chemically stable as compared with other transitionmetal elements in the proximity of the ion source layer 21 and in theresistance change layer 22, and easily causes an intermediate oxidationstate and maintains the intermediate oxidation state easily as well.

In addition, at or near the conduction path formed of the transitionmetal element, three states of “metal state/chalcogen compoundstate/oxide state” whose resistance values are “low/intermediate/high”,respectively, are obtained. The resistance value of the resistancechange layer 22 is determined by a mixture state of the three states,and it is possible to obtain various values (intermediate resistancevalues) by varying the mixture state of the three states.

It should be noted that, in a storage device that performs writing anderasing with use of the resistance change, it is difficult to control aconductance value corresponding to a writing condition for obtaining anintermediate resistance value. FIG. 2 shows a variation in writingconductance value (hereinafter simply referred to as conductance value)when gate voltages (Vgw) of 0.6 V to 2.05 V are applied to existingresistance-change-type storage devices (in this example, three devices).It is seen from FIG. 2 that a variation in conductance value relative tothe gate voltages differs from device to device. Therefore, it isdifficult to achieve a multi-value of a storage unit that includes aplurality of storage devices.

FIG. 3 is a plot showing, in an overlapped manner, conductance values ofthe case where the gate voltages (Vgw) of 0.6 V to 2.05 V are applied to30 storage devices (30 bits) similarly to FIG. 2 (indicated by blacksquare ▪), and showing average values of the conductance values (averageconductance values) at the respective gate voltages (indicated by whitesquare □). To achieve a multi-value of a storage unit, it is necessaryto control the conductance value under a predetermined writing condition(predetermined gate voltage). Specifically, first, it is preferable thatthe conductance value gradually vary relative to the gate voltages. Thisis because it is difficult to finely control the conductance values ofmultiple bits necessary for achieving the multi-value in the storagedevice in which the conductance value abruptly varies in response to aslight variation in gate voltage as can be seen from FIG. 3. Second, itis preferable that the variation in conductance value between thedevices at each gate voltage be small. For example, it can be said that,as illustrated in FIG. 3, it is necessary for a width (L) of theconductance values at the gate voltage 1.4 V to be decreased.

Although details will be described in a working example, thecontrollability of the conductance value and the variation inconductance value between the devices are improved by adjusting thevolume resistivity of the ion source layer 21 to be in a range fromabout 150 mΩ·cm to about 12000 mΩ·cm both inclusive as described above.It is to be noted that, when the volume resistivity of the ion sourcelayer 21 is lower than about 150 mΩ·cm, the variation in conductancevalue is great when writing is performed under the same condition. Whenthe volume resistivity is greater than about 12000 mΩ·cm, a current or avoltage necessary for writing is excessively increased, and thus writingis inhibited.

More preferably, for a film thickness (for example, about 10 nm to about15 nm both inclusive) of the ion source layer 21 used in theminiaturized storage device 1, the volume resistivity may be about 450mΩ·cm to about 3000 mΩ·cm both inclusive. When an initial resistancevalue of the ion source layer 21 is small, an operating current of thestorage device 1 may be increased. The initial resistance value of theion source layer 21 is proportional to the product of the volumeresistivity and the film thickness of the ion source layer 21. That is,when the volume resistivity is decreased, it is necessary to increasethe film thickness in order to obtain the same resistance value. In viewof this, when the film thickness of the ion source layer 21 is set tothe film thickness mentioned above (about 10 nm to about 15 nm bothinclusive, for example), the resistivity may be set to about 450 mΩ·cmor more to allow the operating current to have a proper value. Inaddition, since the voltage necessary for writing is increased when theresistance value of the ion source layer 21 is great, the volumeresistivity of the ion source layer 21 may be preferably about 3000mΩ·cm or lower.

It is to be noted that, as long as an effect of an embodiment of thetechnology is not impaired, the ion source layer 21 may contain elementsother than those mentioned above, such as manganese (Mn), cobalt (Co),iron (Fe), nickel (Ni), platinum (Pt), and Si, for example. Preferably,the ion source layer 21 may not contain aluminum (Al) and copper (Cu).As described above, in order to achieve the multi-value recording, it ispreferable that the variation in conductance value between the devicesat each gate voltage be small, and that the variation in conductancevalue relative to the gate voltage be gradual. For these reasons,preferably, the ion source layer 21 may be made of an element which isdifficult to be transferred by application of an electric field(application of a gate voltage). However, the above-mentioned Al and Cuare high in mobility at the time of voltage application and thereforeare likely to transfer in the above-described metal chalcogenide, whichmakes it easier to vary the conductance value consequently.

The resistance change layer 22 may contain at least any one of a metaloxide, a metal nitride, and a metal oxynitride. In this embodiment, theresistance change layer 22 may be provided in contact with the lowerelectrode 10. The resistance change layer 22 may have a resistance valuewhich is varied when a predetermined voltage is applied between thelower electrode 10 and the upper electrode 30. A metal material of theresistance change layer 22 is not specifically limited as long as theresistance change layer 22 has a high resistance of several MΩ toseveral hundred GΩ at an initial state, for example. For example, when ametal oxide is used as a material of the resistance change layer 22,desirably, metallic elements such as Zr, Hf, Al, and rare-earth elementswhich allow formation of metal oxides having high resistance, that is, alarge band gap may be used. Also, when a metal nitride is used as amaterial of the resistance change layer 22, desirably, metallic elementssuch as Zr, Hf, Al, and rare-earth elements may be used, since suchelements achieve a resistance value of several MΩ to several hundred GΩand are likely to have a high resistivity at the time of an eraseoperation in which the conduction path is oxidized by transfer ofoxygen. Likewise, when a metal oxynitride is used as a material of theresistance change layer 22, the metallic elements which achieve theresistance value of several MΩ to several hundred GΩ may be used. Whilea film thickness of the resistance change layer 22 is not specificallylimited as long as the above-described device resistance of several MΩto several hundred GΩ is achieved and while an optimal value variesdepending on a size of a device and the resistance value of the ionsource layer 21, the film thickness of the resistance change layer 22may be preferably about 1 nm to about 10 nm both inclusive, for example.

It is to be noted that the formation of the resistance change layer 22is optional. In a manufacturing process of the storage device 1, thetransition metal element and oxygen contained in the ion source layer 21are combined with each other, and a metal oxide film corresponding tothe resistance change layer 22 is formed naturally on the lowerelectrode 10. Otherwise, an oxide film formed by application of avoltage bias in an erase direction may be an equivalent of theresistance change layer 22.

Similarly to the lower electrode 10, while existing semiconductor wiringmaterials may be used to form the upper electrode 30, preferably, astable material that does not react with the ion source layer 21 evenwhen subjected to post annealing may be used.

In the storage device 1 according to the present embodiment, when avoltage pulse or a current pulse is applied through the lower electrode10 and the upper electrode 30 from a power source circuit 60 (pulseapplier), electrical characteristics (resistance value) of the storagelayer 20 is varied, and thus writing, erasing, and further reading outof information are performed. Such an operation is specificallydescribed below.

First, a positive voltage may be applied to the storage device 1 havinga high-resistive initial state so that the upper electrode 30 side mayhave a positive potential and the lower electrode 10 side may have anegative potential, for example. Consequently, the transition metalelement in the ion source layer 21 is ionized and transferred to thelower electrode 10 side, or a cathode reaction on the lower electrode 10side is caused by oxygen ions transferred from the lower electrode 10side, whereby reduction reaction is caused at the resistance changelayer 22 formed on an interface of the lower electrode 10. Thisgenerates portions where oxygen defect concentration is increased. Whenthe portions having the high oxygen defect concentration, or theportions having a low oxidation state, are connected to each other, aconduction path is formed in the resistance change layer 22, and theresistance value of the resistance change layer 22 becomes lower(low-resistance state) than the resistance value (high resistance state)at the initial state.

Thereafter, even when the positive voltage is removed and the voltageapplication is stopped for the storage device 1, the low-resistancestate is maintained. Thus, information is written. When the storagedevice 1 is used in a storage unit such as a so-called PROM(programmable read only memory) that allows writing only once, recordingis completed with only the above-mentioned recording step.

On the other hand, an erasing step is necessary when the storage device1 is used in storage units such as a RAM (random access memory) and anEEPROM (electronically erasable and programmable read only memory) thatallow erasing. In the erasing step, a negative voltage may be applied tothe storage device 1 so that the upper electrode 30 side may have anegative potential and the lower electrode 10 side may have a positivepotential, for example. Consequently, an anode reaction is caused at theconduction path of the portions having the high oxygen defectconcentration, or the portions having the low oxidation state, whichconfigure the conduction path formed in the resistance change layer 22,whereby transition metal ions are oxidized and transferred to the ionsource layer 21 side. Otherwise, oxygen ions are transferred from theion source layer 21 to the proximity of the conduction path of theresistance change layer 22, and thus the oxygen defect concentration isdecreased or the oxidation state is increased at the conduction path.Consequently, the conduction path is disconnected, and the resistancevalue of the resistance change layer 22 is changed from thelow-resistance state to the high resistance state.

Thereafter, even when the negative voltage is removed and the voltageapplication is stopped at the storage device 1, the high resistancevalue is maintained. Thus, the information written therein is erased. Byrepeating the above-mentioned steps, it is possible to repeatedlyperform writing of information to the storage device 1 and erasing ofthe information written in the storage device 1.

In the above-mentioned storage device 1, for example, when a state wherethe resistance value is high corresponds to information “0” and a statewhere the resistance value is low corresponds to information “1”, it ispossible to change “0” to “1” in the step of recording information byapplication of a positive voltage, and to change “1” to “0” in the stepof erasing information by application of a negative voltage. It is to benoted that, in this instance, the operation that lowers the resistanceof the storage device and the operation that increases the resistance ofthe storage device correspond to the writing operation and the eraseoperation, respectively, but this relationship may be reversed.

In the present embodiment, controlling a voltage at the time ofapplication of a bias voltage to the lower electrode 10 side,controlling a limiting resistor or a gate voltage of a drive MOStransistor, or the like in a writing operation allows control of theso-called “writing resistance” and adjustment of the intermediateresistance value (writing conductance value). In addition, in theerasing operation, adjusting a magnitude of the bias voltage, thelimiting resistor, a current value with use of the gate voltage of theMOS transistor, or the like allows control of the intermediateresistance value. Thus, not only two but also multi-valued memory isachieved.

For example, intermediate resistance values between the above-mentionedtwo resistance values of “0” and “1” may be adjusted to add, forexample, two levels, and the respective levels may be defined as “00”,“01”, “10”, and “11”. In this case, it is possible to perform recordingof four values. That is, it is possible to record 2-bit information perdevice.

In the storage device 1 of the present embodiment, the volumeresistivity of the ion source layer 21 is set to fall in a range fromabout 150 mΩ·cm to about 12000 mΩ·cm both inclusive as described above,making it possible to improve the controllability of the conductancevalue and the variation in conductance value between the devices.

A method of manufacturing the storage device 1 of the present embodimentis described below.

First, the lower electrode 10 which may be made of TiN, for example, isformed on a substrate on which a CMOS circuit such as a selecttransistor is formed. Then, if necessary, reverse sputtering or the likemay be performed to remove oxide etc., on the surface of the lowerelectrode 10. Subsequently, the resistance change layer 22, the ionsource layer 21, and the upper electrode 30 are sequentially formed in asputtering apparatus with use of targets having compositions appropriatefor the materials of the respective layers while replacing the targets.An electrode diameter may be about 50 nm φ to about 300 nm φ bothinclusive. An alloy film may be formed together with use of targets ofrespective constituent elements.

After the films up to the upper electrode 30 are formed, a wiring layer(not illustrated) to be connected to the upper electrode 30 is formed,and all of the storage devices 1 and a contact section configured toobtain a common potential are connected to each other. Thereafter, postannealing is performed on the laminated film. Thus, the storage device 1illustrated in FIG. 1 is completed.

In the storage device 1, as described above, a voltage may be applied insuch a manner that the upper electrode 30 and the lower electrode 10have a positive potential and a negative potential, respectively,whereby the conduction path is formed in the resistance change layer 22.Consequently, the resistance value of resistance change layer 22 isdecreased, and writing is performed. Next, a voltage having a polarityopposite to that in the writing is applied to each of the upperelectrode 30 and the lower electrode 10, whereby the metallic element inthe conduction path formed in the resistance change layer 22 is ionizedand transferred to the ion source layer 21. Otherwise, the oxygen ionstransfer from the ion source layer 21 to the resistance change layer 22,in particular, to the conduction path of the resistance change layer 22.Consequently, the oxygen defect concentration is decreased or theoxidation state is increased, and thus the conduction path isdisconnected. As a result, the resistance value of the resistance changelayer 22 is increased, and thus erasing is performed. Further, thevoltages to be applied at the time of writing and erasing are adjustedto control the intermediate resistance value, and thus the multi-valuerecording is achieved.

For example, in existing miniaturized storage devices, a storage devicehas been reported that has a “lower electrode/storage layer/upperelectrode” configuration and in which an RRAM material containing oxygenand a transition metal element is used for a storage layer. Inminiaturized storage devices, since a driving current of a transistor isdecreased and a driving current for writing is decreased, a resistancevalue in a low-resistance state is even further increased, and aninterval of resistance value (resistance interval) between thelow-resistance state and the high resistance state is narrowed. In orderto achieve the multi-value recording in memories that perform writingand erasing with use of the resistance change as described above, it isnecessary to control an intermediate resistance value (conductancevalue) between the low-resistance and the high resistance. Specifically,in order to achieve the multi-value operation, it is necessary to dividethe narrow resistance interval into four levels (2 bit/cell), eightlevels (3 bit/cell), or the like, and to control the conductance valuesthat correspond to the resistance values, for example.

However, a storage unit is configured of a plurality of storage devices,and there is an issue in existing storage devices that the conductancevalues at respective gate voltages differ between the devices asillustrated in FIG. 2. In addition, as illustrated in FIG. 3, uponapplication of an electric field, specifically, upon application of avoltage between electrodes that are opposed to each other with a storagelayer therebetween, the conductance value is greatly varied with only aslight variation in applied voltage when the voltage applied thereto(for example, gate voltage) is greater than 1.1 V. Such a greatvariation in conductance value in response to the application of lowvoltage has made a control of an intermediate resistance value of astorage device difficult. In particular, there is an issue that, in aminiaturized storage device whose resistance interval between thelow-resistance state and the high resistance state is narrow, a finecontrol of resistance value is difficult. Under such circumstances, ithas been difficult to achieve the multi-value in a storage unit thatincludes the existing storage devices.

In contrast, in the storage device 1 according to the presentembodiment, the movable element is used for the material of the ionsource layer 21 configuring the storage layer 20, and the volumeresistivity of the ion source layer 21 is in a range from about 150mΩ·cm to about 12000 mΩ·cm both inclusive. Consequently, the variationin conductance value in response to each applied voltage is decreased,and thus the controllability of conductance value is improved.

Therefore, in the storage device 1 according to the present embodiment,the ion source layer 21 contains the movable element and has the volumeresistivity of about 150 mΩ·cm to about 12000 mΩ·cm both inclusive.Thus, the variation in conductance value caused by the variation inapplied voltage is decreased. Consequently, the controllability of theconductance value of the storage device 1 is improved, and the variationin conductance value between the plurality of devices is suppressed. Asa result, it is possible to provide a storage unit that allowsmulti-value recording.

1-2. Storage Unit

The plurality of storage devices 1 described above may be disposed, forexample, in column or in matrix to configure a storage unit (memory). Ifnecessary, each of the storage devices 1 may be connected to a diode ora MOS transistor for device selection to configure a memory cell, andfurther, may be connected to a sense amplifier, an address decoder, awriting circuit, an erasing circuit, a reading out circuit, etc.,through wiring lines.

FIG. 4 and FIG. 5 each show an exemplary storage unit (memory cellarray) in which the plurality of the storage devices 1 are disposed inmatrix, wherein FIG. 4 shows a cross-sectional configuration thereof andFIG. 5 shows a planar configuration thereof. In the memory cell array, awiring line connected to the lower electrode 10 side and a wiring lineconnected to the upper electrode 30 side are provided to cross eachother in each of the storage devices 1, and the storage devices 1 aredisposed in the proximity of respective intersections of the wiringlines, for example.

Each of the storage devices 1 shares the resistance change layer 22, theion source layer 21, and the upper electrode 30. That is, the resistancechange layer 22, the ion source layer 21, and the upper electrode 30 areeach configured of a layer (same layer) common to the storage devices 1.The upper electrode 30 serves as a plate electrode PL common to adjacentcells.

On the other hand, the lower electrode 10 is separately provided foreach of the memory cells and is thus electrically separated from eachother between adjacent cells. Thus, the storage devices 1 of the memorycell are defined at respective positions corresponding to the lowerelectrodes 10. The lower electrodes 10 are connected to respective MOStransistors Tr for cell selection, and the storage devices 1 areprovided above the MOS transistors Tr.

Each of the MOS transistors Tr includes a source-drain region 43 and agate electrode 44 that are formed in a region separated by deviceseparation layers 42 in the substrate 41. A side wall insulation layeris formed on a wall face of the gate electrode 44. The gate electrode 44serves also as a word line WL that is one of address wiring lines of thestorage device 1. One of a source region and a drain region of thesource-drain region 43 of the MOS transistor Tr is electricallyconnected to the lower electrode 10 of the storage device 1 through aplug layer 45, a metal wiring layer 46, and a plug layer 47. The otherof the source region and the drain region of the source-drain region 43of the MOS transistor Tr is connected to the metal wiring layer 46through the plug layer 45. The metal wiring layer 46 is connected to abit line BL that is the other of the address wiring lines of the storagedevice 1 (see FIG. 5). It is to be noted that, in FIG. 5, active regions48 of the MOS transistor Tr are denoted by dashed lines, and a contactsection 51 is connected to the lower electrode 10 of the storage device1 and a contact section 52 is connected to the bit line BL.

In the memory cell array, when a gate of the MOS transistor Tr is placedinto an on state by the word line WL to apply a voltage to the bit lineBL, the voltage is applied to the lower electrode 10 of a selectedmemory cell through the source and drain of the MOS transistor Tr. Here,when a polarity of the voltage applied to the lower electrode 10 isnegative relative to a potential of the upper electrode 30 (plateelectrode PL), the resistance value of the storage device 1 becomes alow-resistance state as described above. Thus, information is written tothe selected memory cell. Next, when a voltage which is positive inpotential relative to the potential of the upper electrode 30 (plateelectrode PL) is applied to the lower electrode 10, the resistance valueof the storage device 1 again becomes a high-resistance state.Consequently, the information written in the selected memory cell iserased. To read out the written information, a memory cell may beselected by the MOS transistor Tr, and a predetermined voltage orcurrent may be applied to the selected cell, for example. A current or avoltage that differs depending on the resistance state of the storagedevice 1 at this time may be detected through a sense amplifier or thelike connected via the bit line BL or plate electrode PL. It is to benoted that the voltage or the current applied to the selected memorycell is made smaller than a threshold level of a voltage or the like atwhich the state of the resistance value of the storage device 1 changes.

The storage unit according to the present embodiment is applicable tovarious kinds of memory units as described above. For example, thestorage unit according to the present embodiment is applicable to anymemory such as PROM that allows writing only once, EEPROM that allowselectrical erasing, or RAM and the like that allow high-speed writing,erasing, and reproducing.

2. Working Example

Specific working examples of an embodiment of the present disclosure aredescribed below.

(Experiments)

The method of manufacturing the storage device 1 described above wasused to fabricate samples (Experiments 1-1 to 1-6). First, after thelower electrode 10 made of TiN and including a transistor incorporatedin a foundation was cleaned by reverse sputtering, Al having a thicknessof 2 nm was formed and oxidized by oxygen plasma to form AlOx, so as toform the resistance change layer 22. Next, for the ion source layer 21,reactive sputtering was performed using Zr60Te40 (atom % ratio) in Arprocess gas mixed with oxygen at a flow ratio of, for example, argon(Ar) (sccm)/oxygen (sccm)=75/5. In this manner, a Zr60Te40-Ox filmhaving volume resistivity (mΩ·cm) of 17.8 and a film thickness of 45 nmwas formed. Subsequently, W having a thickness of 30 nm was formed toform the upper electrode 30. Finally, heat treatment was performed for 2hours at 320 degrees Centigrade and then patterning was performed tofabricate each storage device 1 (Experiments 1-1 to 1-6). It is to benoted that the volume resistivity was obtained by the following method.First, in advance, the ion source layer 21 was formed by theabove-mentioned method on a silicon wafer having an oxide film, whichwas then taken out in the atmosphere. Next, probes were directly appliedto the ion source layer 21 to measure a resistance value by thefour-point probe method. Then, a value thus measured and a value of athickness of the ion source layer 21 measured by a step gauge were usedto obtain the volume resistivity. The compositions of the Experiments1-1 to 1-6 are described below in the order of “lowerelectrode/resistance change layer/ion source layer/upper electrode”.

-   (Experiment 1-1) TiN/Al (2 nm) —Ox/Zr60Te40-Ox (45 nm, 75/5)/W (30    nm); 17.8 mΩ·cm-   (Experiment 1-2) TiN/Al (2 nm) —Ox/Zr50Te50-Ox (45 nm, 75/5)/W (30    nm); 150 mΩ·cm-   (Experiment 1-3) TiN/Al (2 nm) —Ox/Zr46Te54-Ox (45 nm, 75/5)/W (30    nm); 625 mΩ·cm-   (Experiment 1-4) TiN/Al (2 nm) —Ox/Zr50Te50-Ox (45 nm, 75/7)/W (30    nm); 2947 mΩ·cm-   (Experiment 1-5) TiN/Al (2 nm) —Ox/Zr40Te60-Ox (45 nm, 75/5)/W (30    nm); 12190 mΩ·cm-   (Experiment 1-6) TiN/Al (2 nm) —Ox/Zr30T70-Ox (45 nm, 75/3)/W (30    nm); 21291 mΩ·cm

The 30-bit memory arrays 2 which are configured of the above-mentionedrespective samples (Experiments 1-1 to 1-6) were fabricated, and writingoperation was performed. Specifically, the writing voltage was set to3.5 V, and the gate voltage was increased by 0.05 V at a time from 0.6 Vto 2.05 V to measure the variation in conductance value relative to thegate voltages in the case of 30 bits. Results are illustrated in FIG. 6.In addition, an average value of the conduction values in each of theExperiments 1-1 to 1-6 was obtained (indicated by white square □), and avariation in average conductance value depending on the difference involume resistivity (Experiments 1-1 to 1-6) is illustrated in FIG. 7.

It is seen from FIG. 7 that, in each of the Experiments 1-2 to 1-5 inwhich the volume resistivity was 150 mΩ·cm to 12190 mΩ·cm, theconductance value was gradually increased as the gate voltage wasincreased. In contrast, in the Experiment 1-1 in which the volumeresistivity was 17.8 mΩ·cm, a variation in increase of the conductancevalue with the increase in gate voltage was great, and some conductancevalues were reversed. In the Experiment 6 in which the volumeresistivity was 21291 mΩ·cm, the conductance value did not vary evenwhen the gate voltage was increased. In other words, it is seen thatsince a voltage or a current necessary for writing was excessivelygreat, typical drive conditions are not sufficient to perform writing.

As mentioned earlier, as a first condition for achieving the multi-valueof a storage unit, it is preferable that the variation in averageconductance value of the plurality of storage devices 1 at each writingcondition (each gate voltage) be gradual. If the average conductancevalue steeply varies relative to the gate voltage, then it becomesdifficult to finely control, in a narrow range, the conductance valuesof the plurality of storage device 1 by the gate voltage. Accordingly,it is preferable that the variation in conductance value be gradualrelative to the variation in gate voltage. Specifically, it ispreferable that the conductance value be gradually increased with theincrease in gate voltage without being reversed, as illustrated in theExperiments 1-2 to 1-5. Here, for example, when a range of the gatevoltage (Vgw) between which the average conductance values range from 3μS to 8 μS was defined as ΔVgw, values thereof in the Experiments 1-1 to1-5 were as illustrated in Table 1. It is to be noted that theExperiment 1-6 was skipped since no variation in conductance value wasobserved.

TABLE 1 Volume Resistivity (mΩ · cm) ΔVgw Experiment 1-1 17.8 0.20Experiment 1-2 150 0.25 Experiment 1-3 625 0.25 Experiment 1-4 2947 0.45Experiment 1-5 12190 0.55

It is seen from Table 1 that ΔVgw was increased as the volumeresistivity of the ion source layer 21 was increased. In other words, itcan be said that as ΔVgw is increased, it becomes easier to control theconductance values by the gate voltage when writing is performed at theplurality of conductance values in the range from 3 μS to 8 μS. On thecontrary, ΔVgw was small in the Experiment 1-1 where the volumeresistivity was small, and it can be said that the conductance value islikely to be varied with only a slight difference in gate voltage, thatis, it can be said that it is difficult to control the conductance valueby the gate voltage, and to achieve the multi-value in a miniaturizedstorage device that necessitates a control in the narrow range. Giventhe above, it is seen that when the volume resistivity of the ion sourcelayer is about 150 mΩ·cm to about 12000 mΩ·cm both inclusive, it ispossible to control the conductance value at each gate voltage. It is tobe noted that the writing current was 30 μA or lower in the Experiments1-1 to 1-5 in the range in which the conductance value was 8 μS or lowerand in which the gate voltage was 1 V to 2 V. That is, it is seen thatthe multi-value recording by a low current is possible when the volumeresistivity of the ion source layer 21 falls within the above-mentionedrange.

In addition, as a second condition for achieving the above-describedmulti-value in a storage unit, it is preferable that the conductancevalues of the plurality of devices under each writing condition (eachgate voltage) be uniform, and the variation thereof be small. FIG. 8shows, in standard deviations, the variations in conductance value in 30bits relative to the gate voltages in the respective Experiments 1-1 to1-5. It is to be noted that, similarly to Table 1, the Experiment 6 wasskipped since no variation in conductance value was observed. From FIG.8, it is seen that when compared at the same gate voltage, the greaterthe volume resistivity in the experiment, the smaller the variation inconductance value therein.

Further, FIG. 9 shows, in standard deviations, the variations inconductance value when, in the respective Experiments 1-1 to 1-5,writing was performed on all of 30 bits by the same gate voltage and theaverage conductance values of all of the samples were set to the samevalue. From FIG. 9, it is possible to compare the variation between thestorage devices 1 in each of the Experiments 1-1 to 1-5 in the casewhere the average conductance values were set to the same value in thoseexperiments. It is to be noted that the Experiment 1-6 was skipped forthe reason similar to that of Table 1 and FIG. 8.

In addition, other than the storage devices 1 of the Experiments 1-1 to1-5, samples (Experiments 2-1 to 2-5) each including the ion sourcelayer 21 having a configuration of HfTeX-Ox in which Al or Cu was usedas X were fabricated, the variation in conductance value of each ofwhich is illustrated in FIG. 9. Compositions of the Experiments 2-1 to2-5 are illustrated below in the order of “lower electrode/resistancechange layer/ion source layer/upper electrode”. It is to be noted thatmanufacturing processes of the Experiments 2-1 to 2-5 were based onthose of the above-mentioned Experiments 1-1 to 1-6.

-   (Experiment 2-1) TiN/Al (2 nm) —Ox/Hf43Te47Al10-Ox (45 nm, 75/5)/W    (30 nm); 20.1 mΩ·cm-   (Experiment 2-2) TiN/Al (2 nm) —Ox/Hf43Te47Al10-Ox (45 nm, 75/5)/W    (30 nm); 610 mΩ·cm-   (Experiment 2-3) TiN/Al (2 nm) —Ox/Hf53Te39Cu8-Ox (45 nm, 75/7)/W    (30 nm); 10 mΩ·cm-   (Experiment 2-4) TiN/Al (2 nm) —Ox/Hf42Te45Cu13-Ox (45 nm, 75/5)/W    (30 nm); 500 mΩ·cm

It is seen from FIG. 9 that even when the average writing conductancevalues in 30 bits were the same value in the Experiments 1-1 to 1-5, thegreater the volume resistivity of the ion source layer 21, the smallerthe variation in writing conductance value in each of the storagedevices 1. In particular, in the low conductance region of 3 μS to 8 μS,the standard deviation of the writing conductance value of the storagedevices 1 in the Experiment 1-1 was greater than those of the storagedevices 1 in the Experiments 1-2 to 1-5. That is, it can be said thatthe storage devices 1 of the Experiment 1-1 cause great variation andare unsuitable for the multi-value recording. In addition, the standarddeviation of the writing conductance value in each of the Experiments2-1 to 2-4 where Al or Cu was added to the ion source layer was greaterthan those of the Experiments 1-2 to 1-5 even when the volumeresistivity is 150 mΩ·cm or more. That is, it is seen that when Al or Cuis added to the ion source layer 21, the variation in writingconductance value tends to be increased.

From the above results, it is seen that, in a resistance-change typestorage device, it is possible to improve the controllability of thewriting conductance value and to suppress the variation in conductancevalue between the plurality of devices by setting the volume resistivityof the ion source layer 21 to fall in the range from about 150 mΩ·cm toabout 12000 mΩ·cm both inclusive. That is, by setting the volumeresistivity of the ion source layer 21 to fall in the range from about150 mΩ·cm to about 12000 mΩ·cm both inclusive, it is possible to providethe storage unit that allows the multi-value recording. Incidentally,from the results of the Experiments 2-1 to 2-4 illustrated in FIG. 9, itis seen that the storage device more suitable for the multi-valuerecording may be achieved when Al and Cu are not used as the materialsof the ion source layer 21. In addition, while only the experimentswhere the resistance change layer is made of Al-Ox are illustrated here,a similar effect is obtained even in the case where the resistancechange layer of the storage device 1 of the present embodiment isconfigured of an oxide film, a nitride film, or an oxynitride film ofZr, Hf, Y, or the like.

Hereinabove, while the present disclosure has been described withreference to the example embodiment and the working example, the presentdisclosure is not limited to the above-mentioned embodiment and soforth, and various modifications may be made.

For example, while, in the above-mentioned embodiment and workingexample, the configurations of the storage device 1 and the memory cellarray 2 are described in detail, all of the layers are not necessarilybe included, and other layers may be further included. In addition, thematerials of the layers, the method of forming the films, and the filmformation conditions described in the above-mentioned embodiment and soforth are not limitative, and other materials and other methods offorming the films may also be adopted. For example, an additive elementmay be used in the ion source layer 21 to the extent that theabove-mentioned composition ratio, demand characteristics for themulti-value memory, or the like is not impaired.

Further, the storage device 1 according to any of the above-mentionedembodiment and so forth may have a structure in which the positions ofthe ion source layer 21 and the resistance change layer 22 are reversedupside down. Also, a cross point structure or system may be employed inwhich an appropriate diode is used in combination in order to increasememory capacity. Further, the memory device may also be laminated in avertical direction. In this manner, the storage device 1 according toany of the above-mentioned embodiment and so forth is applicable tovarious memory structures.

Furthermore, the technology encompasses any possible combination of someor all of the various embodiments described herein and incorporatedherein.

It is possible to achieve at least the following configurations from theabove-described example embodiments of the disclosure.

(1) A storage device, including:

a first electrode;

a storage layer including an ion source layer; and

a second electrode,

the first electrode, the storage layer, and the second electrode beingprovided in this order,

wherein the ion source layer contains a movable element, and has avolume resistivity of about 150 mΩ·cm to about 12000 mΩ·cm bothinclusive.

(2) The storage device according to (1), wherein the ion source layerhas the volume resistivity of about 450 mΩ·cm to about 3000 mΩ·cm bothinclusive.(3) The storage device according to (1) or (2), wherein the movableelement is positively or negatively ionized by application of anelectric field.(4) The storage device according to (3), wherein the ion source layercontains, as the movable element positively ionized, one or moreelements selected from a group consisting of Group 3 elements, Group 4elements, and Group 5 elements of the Periodic Table.(5) The storage device according to (4), wherein the movable elementpositively ionized is one of titanium (Ti), zirconium (Zr), and hafnium(Hf).(6) The storage device according to (3), wherein the ion source layercontains, as the movable element negatively ionized, one or moreelements selected from Group 16 elements of the Periodic Table.(7) The storage device according to (6), wherein the movable elementnegatively ionized is one of sulfur (S), selenium (Se), and tellurium(Te).(8) The storage device according to any one of (1) to (7), wherein theion source layer is free from aluminum (Al) and copper (Cu).(9) The storage device according to any one of (1) to (8), wherein thestorage layer includes a resistance change layer provided closer to thefirst electrode than the second electrode.(10) The storage device according to (9), wherein the resistance changelayer is configured of one of a metal oxide film, a metal nitride film,and a metal oxynitride film.(11) The storage device according to any one of (1) to (10), wherein theresistance change layer has a resistance value that varies in responseto formation of a low-resistance section, the low-resistance sectionbeing formed in the resistance change layer by containing the movableelement or an oxygen defect upon application of a voltage to the firstelectrode and the second electrode.(12) A storage unit provided with a plurality of storage devices and apulse applier that selectively applies one of a voltage pulse and acurrent pulse to the storage devices, the storage devices eachincluding:

a first electrode;

a storage layer including an ion source layer; and

a second electrode,

the first electrode, the storage layer, and the second electrode beingprovided in this order,

wherein the ion source layer contains a movable element, and has avolume resistivity of about 150 mΩ·cm to about 12000 mΩ·cm bothinclusive.

It should be understood by those skilled in the art that variousmodifications, combinations, sub-combinations and alterations may occurdepending on design requirements and other factors insofar as they arewithin the scope of the appended claims or the equivalents thereof.

What is claimed is:
 1. A storage device, comprising: a first electrode;a second electrode; and a storage layer between the first electrode andthe second electrode, the storage layer including an ion source layer,wherein the ion source layer is positively or negatively ionized byapplication of an electric field, and wherein the ion source layer has avolume resistivity of at least 150 mΩ·cm and less than or equal to 12000mΩ·cm such that the storage layer has a low resistance statecorresponding to first stored information, a high resistance statecorresponding to second stored information, and at least oneintermediate resistance state, between the low resistance state and thehigh resistance state, corresponding to third stored information.
 2. Thestorage device according to claim 1, wherein the ion source layer hasthe volume resistivity of about 450 mΩ·cm to about 3000 mΩ·cm bothinclusive.
 3. The storage device according to claim 1, wherein the ionsource layer contains oxygen.
 4. The storage device according to claim3, wherein the ion source layer contains one or more elements selectedfrom the group consisting of Group 4 elements, Group 5 elements, andGroup 6 elements of the Periodic Table.
 5. The storage device accordingto claim 1, wherein the ion source layer is selected from the groupconsisting of titanium (Ti), zirconium (Zr), and hafnium (Hf)
 6. Thestorage device according to claim 1, wherein the ion source layercontains one or more elements selected from the group consisting ofGroup 16 elements of the Periodic Table.
 7. The storage device accordingto claim 1, wherein the ion source layer that is negatively ionized isselected from the group consisting of sulfur (S), selenium (Se), andtellurium (Te).
 8. The storage device according to claim 1, wherein thestorage layer includes a resistance change layer provided closer to thefirst electrode than the second electrode.
 9. The storage deviceaccording to claim 8, wherein the resistance change layer is configuredfrom a metal oxide film, a metal nitride film, or a metal oxynitridefilm
 10. The storage device according to claim 8, wherein the resistancechange layer has a resistance value that varies in response to anapplication of a voltage to the first electrode and the secondelectrode.
 11. A storage unit with a plurality of storage devices and apulse applier that selectively applies a voltage pulse or a currentpulse to the storage devices, the storage devices each comprising: afirst electrode; a second electrode; and a storage layer between thefirst electrode and the second electrode, the storage layer including anion source layer wherein the ion source layer is positively ornegatively ionized by application of an electric field, and wherein theion source layer has a volume resistivity of at least 150 mΩ·cm and lessthan or equal to 12000 mΩ·cm such that the storage layer has a lowresistance state corresponding to first stored information, a highresistance state corresponding to second stored information, and atleast one intermediate resistance state, between the low resistancestate and the high resistance state, corresponding to third storedinformation.
 12. The storage unit according to claim 11, wherein the ionsource layer has the volume resistivity of about 450 mΩ·cm to about 3000mΩ·cm both inclusive.
 13. The storage unit according to claim 11,wherein the ion source layer contains oxygen.
 14. The storage unitaccording to claim 13, wherein the ion source layer contains one or moreelements selected from the group consisting of Group 4 elements, Group 5elements, and Group 6 elements of the Periodic Table.
 15. The storageunit according to claim 11, wherein the ion source layer is selectedfrom the group consisting of titanium (Ti), zirconium (Zr), and hafnium(Hf).
 16. The storage unit according to claim 11, wherein the ion sourcelayer contains one or more elements selected from the group consistingof Group 16 elements of the Periodic Table.
 17. The storage unitaccording to claim 11, wherein the ion source layer that is negativelyionized is selected from the group consisting of sulfur (S), selenium(Se), and tellurium (Te).
 18. The storage unit according to claim 11,wherein the storage layer includes a resistance change layer providedcloser to the first electrode than the second electrode.
 19. The storageunit according to claim 18, wherein the resistance change layer isconfigured from a metal oxide film, a metal nitride film, or a metaloxynitride film.
 20. The storage unit according to claim 18, wherein theresistance change layer has a resistance value that varies in responseto an application of a voltage to the first electrode and the secondelectrode.